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ISL6744
Data Sheet July 2004 FN9147.3
Intermediate Bus PWM Controller
The ISL6744 is a low cost, primary side, double-ended controller intended for applications using full and half-bridge topologies for unregulated DC-DC converters. Typical applications are bus converters and DC transformers. It provides adjustable oscillator frequency, adjustable soft-start, overcurrent shutdown, and precise control of switching frequency and deadtime. This advanced BiCMOS design features low start-up and operating currents, adjustable switching frequency up to 1MHz, 1A FET drivers, and very low propagation delays.
Features
* Precision Duty Cycle and Deadtime Control * 100A Startup Current * Adjustable Delayed Overcurrent Shutdown and Re-Start * Adjustable Oscillator Frequency Up to 2MHz * 1A MOSFET Gate Drivers * Adjustable Soft-Start * Internal Over Temperature Protection * 35ns Control to Output Propagation Delay * Small Size and Minimal External Component Count
Ordering Information
PART NUMBER ISL6744AU ISL6744AUZ (See Note) ISL6744AB ISL6744ABZ (See Note) TEMP. RANGE (C) -40 to 105 -40 to 105 -40 to 105 -40 to 105 PACKAGE 8 Ld MSOP 8 Ld MSOP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) PKG. DWG. # M8.118 M8.118 M8.15 M8.15
* Input Under Voltage Protection * Pb-free available
Applications
* Telecom and Datacom Isolated Power * DC Transformers * Bus Converters
Add -T suffix to part number for tape and reel packaging NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
Pinout
ISL6744 (SOIC, MSOP) TOP VIEW
SS 1 RTD 2 CS 3 CT 4 8 VDD 7 OUTB 6 OUTA 5 GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
Internal Architecture
VDD VBIAS 5.00 V VBIAS
FL
VDD
Q
OUTA
+ BG
UVLO
T Q
OUTB VBIAS 70uA
PWM TOGGLE
INTERNAL OT SHUTDOWN 130 - 150 C
GND
I DCH= 55 x IRTD
2
VBIAS SS CLAMP RTD 2.0 V IRTD + 4.0 V VBIAS 160 uA ON 2.8 V + CT 0.8 V + VALLEY PEAK
S R Q Q S R Q Q
ON
SS
+ + SS CHARGED 3.9 V
15 uA
OC LATCH CLK
ISL6744
Q Q
RESET DOMINANT
50 S RETRIGGERABLE ONE SHOT
SS LOW
+ SS
0.27 V
FAULT LATCH SET DOMINANT
S Q Q S R Q Q
FL
IDCH
R
ON
PWM LATCH SET DOMINANT VBIAS UV 4.65V 4.80V OC DETECT + BG
VBIAS
CS 0.6 V
+ -
SS COMPARATOR CT + -
SS 0.8
Typical Application using ISL6744 - 48V Input DC Transformer, 12V @ 8A Output
SP1 VIN+ QR1 L1 C2 QH L3 T1 R8 C13 C9 C8 RTN C11 QR3 +12
TP1
R10
L2
3
VIN-
C1 T2 R9
R2 CR3
QL C14 R11
QR2
QR4
C12
C3 R1 C7 U1 ISL6700 V DD HB CR4 HO HS LO V SS LI HI TP4 CR1 R5
CR2 TP2 R6
ISL6744
C10
C4 C5 TP5 U2 SS
GND
ISL6744
OUTB OUTA V DD R7 D2 TP6 Q5 C15
CS CT R TD C18
C17 D1 R12 C6
ISL6744
Absolute Maximum Ratings
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20.0V OUTA, OUTB . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VDD Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5V Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A ESD Classification Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .100V Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1000V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) 8 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Maximum Junction Temperature . . . . . . . . . . . . . . . . -55C to 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C
Operating Conditions
Temperature Range ISL6744AU . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to 105C Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . 9-16 VDC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. All voltages are to be measured with respect to GND, unless otherwise specified.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. 9V < VDD< 16V, RTD = 51.1k, CT = 470pF, TA = -40C to 105C (Note 4), Typical values are at TA = 25C TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER SUPPLY VOLTAGE Start-Up Current, IDD Operating Current, IDD
VDD< START Threshold RLOAD, COUTA,B = 0 COUTA,B = 1nF
5.9 5.3 -
2.89 5 6.3 5.7 0.6
175 8.5 6.6 6.3 -
A mA mA V V V
UVLO START Threshold UVLO STOP Threshold Hysteresis CURRENT SENSE Current Limit Threshold CS to OUT Delay CS Sink Current Input Bias Current PULSE WIDTH MODULATOR Maximum Duty Cycle CT to SS Comparator Input Gain SS to SS Comparator Input Gain OSCILLATOR Charge Current RTD Voltage Discharge Current Gain CT Valley Voltage CT Peak Voltage CT Input Impedance (Note 4) (Note 4) (Note 4) (Note 4)
0.55 8 -1
0.6 35 10 -
0.65 1
V ns mA A
-
94 1 0.8
-
% V/V V/V
1.925 45 0.75 2.70 -
160 2 0.8 2.80 -
2.075 65 0.85 2.90 -
A V A/A V V
4
ISL6744
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application schematic. 9V < VDD< 16V, RTD = 51.1k, CT = 470pF, TA = -40C to 105C (Note 4), Typical values are at TA = 25C (Continued) TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER SOFT-START Charging Current SS Clamp Voltage Overcurrent Shutdown Threshold Voltage Overcurrent Discharge Current Reset Threshold Voltage OUTPUT High Level Output Voltage (VOH) Low Level Output Voltage (VOL) Rise Time Fall Time THERMAL PROTECTION Thermal Shutdown Thermal Shutdown Clear Hysteresis, Internal Protection NOTES: (Note 4) (Note 4) (Note 4) (Note 4) (Note 4)
45 3.8 12 0.25
4.0 3.9 15 0.27
68 4.2 23 0.30
A V V A V
VDD - VOUTA or VOUTB, IOUT = -100mA IOUT = 100mA CGATE = 1nF, VDD = 12V CGATE = 1nF, VDD = 12V
-
0.5 0.5 17 20
2.0 1.0 60 60
V V ns ns
-
145 130 15
-
C C C
3. Specifications at -40C are guaranteed by design, not production tested. 4. Guaranteed by design, not 100% tested in production.
5
ISL6744 Typical Performance Curves
65 CT DISCHARGE CURRENT GAIN 1.104
60 DEADTIME (ns) 1.103
55
CT = 1000pF 680pF 470pF 270pF 100pF
50
100
45
40 0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
10
0
10
20
30
RTD CURRENT (mA)
40 50 60 RTD (k)
70
80
90
100
FIGURE 1. OSCILLATOR CT DISCHARGE CURRENT GAIN
FIGURE 2. DEADTIME vs CAPACITANCE
1.103
FREQUENCY (kHz)
100
10
0
100 200 300 400 500 600 700 800 900 1000 CAPACITANCE (pF)
FIGURE 3. CAPACITANCE vs FREQUENCY (RTD = 51.1k)
6
ISL6744 Pin Descriptions
VDD - VDD is the power connection for the IC. To optimize noise immunity, bypass VDD to GND with a ceramic capacitor as close to the VDD and GND pins as possible. The total supply current, IDD, will be dependent on the load applied to outputs OUTA and OUTB. Total IDD current is the sum of the quiescent current and the average output current. Knowing the operating frequency, Fsw, and the output loading capacitance charge, Q, per output, the average output current can be calculated from:
I OUT = 2 * Q * Fsw (EQ. 1)
Functional Description
Features
The ISL6744 PWM is an excellent choice for low cost bridge topologies for applications requiring accurate frequency and deadtime control. Among its many features are 1A FET drivers, adjustable soft-start, overcurrent protection and internal thermal protection, allowing a highly flexible design with minimal external components.
Oscillator
The ISL6744 has an oscillator with a frequency range to 2MHz, programmable using a resistor RTD and capacitor CT. The switching period may be considered to be the sum of the timing capacitor charge and discharge durations. The charge duration is determined by CT and the internal 160A current source. The discharge duration is determined by RTD and CT.
T C 1.25 x10 * C T
4
RTD - This is the oscillator timing capacitor discharge current control pin. A resistor is connected between this pin and GND. The current flowing through the resistor determines the magnitude of the discharge current. The discharge current is nominally 75x this current. The PWM deadtime is determined by the timing capacitor discharge duration. CT - The oscillator timing capacitor is connected between this pin and GND. CS - This is the input to the overcurrent protection comparator. The overcurrent comparator threshold is set at 0.600V nominal. The CS pin is shorted to GND at the end of each switching cycle. Depending on the current sensing source impedance, a series input resistor may be required due to the delay between the internal clock and the external power switch. Exceeding the overcurrent threshold will start a delayed shutdown sequence. Once an overcurrent condition is detected, the soft-start charge current source is disabled. The soft-start capacitor begins discharging through a 15A current source, and if it discharges to less than 3.9V (Sustained Overcurrent Threshold), a shutdown condition occurs and the OUTA and OUTB outputs are forced low. When the soft-start voltage reaches 0.27V (Reset Threshold) a soft-start cycle begins. If the overcurrent condition ceases, and then an additional 50s period elapses before the shutdown threshold is reached, no shutdown occurs. The SS charging current is re-enabled and the soft-start voltage is allowed to recover. GND - Reference and power ground for all functions on this device. Due to high peak currents and high frequency operation, a low impedance layout is necessary. Ground planes and short traces are highly recommended. OUTA and OUTB - Alternate half cycle output stages. Each output is capable of 1A peak currents for driving power MOSFETs or MOSFET drivers. Each output provides very low impedance to overshoot and undershoot. SS - Connect the soft-start timing capacitor between this pin and GND to control the duration of soft-start. The value of the capacitor determines the rate of increase of the duty cycle during start up, controls the overcurrent shutdown delay, and the overcurrent and short circuit hiccup restart period. 7
s
(EQ. 2)
1 T D ---------------------------------------------------------------------------- * R TD * C T CTDishc arg eCurrentGain
s
(EQ. 3)
1 T SW = T C + T D = ----------F SW
s
(EQ. 4)
where TC and TD are the charge and discharge times, respectively, TSW is the oscillator free running period, and FSW is the oscillator frequency. One output switching cycle requires two oscillator cycles. The actual times will be slightly longer than calculated due to internal propagation delays of approximately 5ns/transition. This delay adds directly to the switching duration, but also causes overshoot of the timing capacitor peak and valley voltage thresholds, effectively increasing the peak-to-peak voltage on the timing capacitor. Additionally, if very low charge and discharge currents are used, there will be an increased error due to the input impedance at the CT pin. The maximum duty cycle, D, and deadtime, DT, can be calculated from: D = TC /TS DT = 1- D
Soft-Start Operation
The ISL6744 features a soft-start using an external capacitor in conjunction with an internal current source. Soft-start reduces stresses and surge currents during start-up. The oscillator capacitor signal, CT, is compared to the soft-start voltage, SS, in the SS comparator which drives the PWM latch. While the SS voltage is less than 2.8V, duty cycle is limited. The output pulse width increases as the soft-start capacitor voltage increases up to 2.8V. This has
ISL6744
the effect of increasing the duty cycle from zero to the maximum pulse width during the soft-start period. When the soft-start voltage exceeds 2.8V, soft-start is completed. Soft-start occurs during start-up and after recovery from an overcurrent shutdown. The soft-start voltage is clamped to 4V.
Typical Application
The Typical Application Schematic features the ISL6744 in an unregulated half-bridge DC-DC converter configuration, often referred to as a DC Transformer or Bus Converter. The input voltage is 48V 10% DC. The output is a nominal 12V when the input voltage is at 48V. Since this is an unregulated topology, the output voltage will vary proportionately with input voltage. The load regulation is a function of resistance between the source and the converter output. The output is rated at 8A.
Gate Drive
The ISL6744 is capable of sourcing and sinking 1A peak current, and may also be used in conjunction with a MOSFET driver such as the ISL6700 for level shifting. To limit the peak current through the IC, an external resistor may be placed between the totem-pole output of the IC (OUTA or OUTB pin) and the gate of the MOSFET. This small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the FET's input capacitance.
Circuit Elements
The converter design is comprised of the following functional blocks: Input Filtering: L1, C1, R1 Half-Bridge Capacitors: C2, C3 Isolation Transformer: T1 Primary Snubber: C13, R10 Start Bias Regulator: CR3, R2, R7, C6, Q5, D1 Supply Bypass Components: C15, C4 Main MOSFET Power Switch: QH, QL Current Sense Network: T2, CR1, CR2, R5, R6, R11, C10, C14 Control Circuit: U2, C18, C17, D2 Output Rectification and Filtering: QR1, QR2, QR3, QR4, L2, C9, C8 Secondary Snubber: R8, R9, C11, C12 FET Driver: U1 Bootstrap components for driver: CR4, C5 ZVS Resonant Delay (Optional): L3, C7
Overcurrent Operation
Overcurrent delayed shutdown is enabled once the soft-start cycle is complete. If an overcurrent condition is detected, the soft-start charging current source is disabled and the softstart capacitor is allowed to discharge through a 15A source. At the same time a 50s retriggerable one-shot timer is activated. It remains active for 50s after the overcurrent condition ceases. If the soft-start capacitor discharges to 3.9V, the output is disabled. This state continues until the soft-start voltage reaches 270mV, at which time a new softstart cycle is initiated. If the overcurrent condition stops at least 50s prior to the soft-start voltage reaching 3.9V, the soft-start charging currents revert to normal operation and the soft-start voltage is allowed to recover.
Thermal Protection
An internal temperature sensor protects the device should the junction temperature exceed 145C. There is approximately 15C of hysteresis.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the device. A good ground plane must be employed. VDD should be bypassed directly to GND with good high frequency capacitance.
Design Specifications
The following design requirements were selected for evaluation purposes: Switching Frequency, Fsw: 235 kHz VIN: 48 10% V VOUT: 12 V (nominal) IOUT: 8 A (steady state) POUT: 100W Efficiency: 95% Ripple: 1%
8
ISL6744
Since the converter is operating open loop at nearly 100% duty cycle, the turns ratio, N, is simply the ratio of the input voltage to the output voltage divided by 2.
V IN 48 N = ------------------------ = -------------- = 2 V OUT * 2 12 * 2 (EQ. 5)
nSR nS nP nS nSR
FIGURE 4. TRANSFORMER SCHEMATIC
The factor of 2 divisor is due to the half-bridge topology. Only half of the input voltage is applied to the primary of the transformer. A PC44HPQ20/6 "E-Core" plus a PC44PQ20/3 "I-Core" from TDK were selected for the transformer core. The ferrite material is PC44. The core parameter of concern for flux density is the effective core cross-sectional area, Ae. For the PQ core pieces selected: Ae = 0.62cm2 or 6.2e -5m2 Using Faraday's Law, V = N d/dt, the number of primary turns can be determined once the maximum flux density is set. An acceptable Bmax is ultimately determined by the allowable power dissipation in the ferrite material and is influenced by the lossiness of the core, core geometry, operating ambient temperature, and air flow. The TDK datasheet for PC44 material indicates a core loss factor of ~400 mW/cm3 with a 2000 gauss 100kHz sinusoidal excitation. The application uses a 235kHz square wave excitation, so no direct comparison between the application and the data can be made. Interpolation of the data is required. The core volume is approximately 1.6cm3, so the estimated core loss is
f act 3 mW 235kHz P loss ---------- * cm * --------------- = 0.4 * 1.6 * -------------------- = 1.5 3 f meas 100kHz cm W (EQ. 6)
Transformer Design
The design of a transformer for a half-bridge application is a straightforward affair, although iterative. It is a process of many compromises, and even experienced designers will produce different designs when presented with identical requirements. The iterative design process is not presented here for clarity. The abbreviated design process follows: * Select a core geometry suitable for the application. Constraints of height, footprint, mounting preference, and operating environment will affect the choice. * Determine the turns ratio. * Select suitable core material(s). * Select maximum flux density desired for operation. * Select core size. Core size will be dictated by the capability of the core structure to store the required energy, the number of turns that have to be wound, and the wire gauge needed. Often the window area (the space used for the windings) and power loss determine the final core size. * Determine maximum desired flux density. Depending on the frequency of operation, the core material selected, and the operating environment, the allowed flux density must be determined. The decision of what flux density to allow is often difficult to determine initially. Usually the highest flux density that produces an acceptable design is used, but often the winding geometry dictates a larger core than is indicated based on flux density alone. * Determine the number of primary turns. * Select the wire gauge for each winding. * Determine winding order and insulation requirements. * Verify the design. For this application we have selected a planar structure to achieve a low profile design. A PQ style core was selected because of its round center leg cross section, but there are many suitable core styles available.
1.28W of dissipation is significant for a core of this size. Reducing the flux density to 1200 gauss will reduce the dissipation by about the same percentage, or 40%. Ultimately, evaluation of the transformer's performance in the application will determine what is acceptable. From Faraday's Law and using 1200 gauss peak flux density (B = 2400 gauss or 0.24 tesla)
-6 V IN * T ON 53 * 2 * 10 N = ----------------------------- = ---------------------------------------------------- = 3.56 -5 2 * A e * B 2 * 6.2 * 10 * 0.24
turns (EQ. 7)
Rounding up yields 4 turns for the primary winding. The peak flux density using 4 turns is ~1100 gauss. From EQ. 5, the number of secondary turns is 2. The volts/turn for this design ranges from 5.4V at VIN = 43V to 6.6V at VIN = 53V. Therefore, the synchronous rectifier (SR) windings may be set at 1 turn each with proper FET
9
ISL6744
selection. Selecting 2 turns for the synchronous rectifier windings would also be acceptable, but the gate drive losses would increase. The next step is to determine the equivalent wire gauge for the planar structure. Since each secondary winding conducts for only 50% of the period, the RMS current is
I RMS = I OUT * D = 10 * 0.5 = 7.07 A (EQ. 8)
where D is the duty cycle. Since an FR-4 PWB planar winding structure was selected, the width of the copper traces is limited by the window area width, and the number of layers is limited by the window area height. The PQ core selected has a usable window area width of 0.165 inches. Allowing one turn per layer and 0.020 inches clearance at the edges allows a maximum trace width of 0.125 inches. Using 100 circular mils(c.m.)/A as a guideline for current density, and from EQ. 8, 707c.m. are required for each of the secondary windings (a circular mil is the area of a circle 0.001 inches in diameter). Converting c.m. to square mils yields 555mils2 (0.785 sq. mils/c.m.). Dividing by the trace width results in a copper thickness of 4.44mils (0.112mm). Using 1.3mils/oz. of copper requires a copper weight of 3.4oz. For reasons of cost, 3oz. copper was selected. One layer of each secondary winding also contains the synchronous rectifier winding. For this layer the secondary trace width is reduced by 0.025 inches to 0.100 inches(0.015 inches for the SR winding trace width and 0.010 inches spacing between the SR winding and the secondary winding). The choice of copper weight may be validated by calculating the DC copper losses of the secondary winding. Ignoring the terminal and lead-in resistance, the resistance of each layer of the secondary may be approximated using EQ. 9.
2 R = ---------------------- r 2 t * ln ---- r 1 (EQ. 9)
The primary windings have an RMS current of approximately 5 A (IOUT x NS/NP at ~ 100% duty cycle). The primary is configured as 2 layers, 2 turns per layer to minimize the winding stack height. Allowing 0.020 inches edge clearance and 0.010 inches between turns yields a trace width of 0.0575 inches. Ignoring the terminal and lead-in resistance, and using EQ. 9, the inner trace has a resistance of 4.25m, and the outer trace has a resistance of 5.52m. The resistance of the primary then is 19.5m at 20C. The total DC power loss for the primary at 20C is 489mW. Improved efficiency and thermal performance could be achieved by selecting heavier copper weight for the windings. Evaluation in the application will determine its need. The order and geometry of the windings affects the AC resistance, winding capacitance, and leakage inductance of the finished transformer. To mitigate these effects, interleaving the windings is necessary. The primary winding is sandwiched between the two secondary windings. The winding layout appears below.
FIGURE 4A. TOP LAYER: 1 TURN SECONDARY AND SR WINDINGS
where R = Winding resistance = Resistivity of copper = 669e-9-inches at 20C t = Thickness of the copper (3 oz.) = 3.9e-3 inches r2 = Outside radius of the copper trace = 0.324 or 0.299 inches r1 = Inside radius of the copper trace = 0.199 inches The winding without the SR winding on the same layer has a DC resistance 2.21m. The winding that shares the layer with the SR winding has a DC resistance of 2.65m. With the secondary configured as a 4 turn center tapped winding (2 turns each side of the tap), the total DC power loss for the secondary at 20C is 486mW.
FIGURE 4B. INT. LAYER 1: 1 TURN SECONDARY WINDING
10
ISL6744
0.689 0.358 0.807 0.639
0.403
0.169 0.000 0.000 0.184 0.479 0.774 1.054
FIGURE 4C. INT. LAYER 2: 2 TURNS PRIMARY WINDING
FIGURE 4G. PWB DIMENSIONS
MOSFET Selection
The criteria for selection of the primary side half-bridge FETs and the secondary side synchronous rectifier FETs is largely based on the current and voltage rating of the device. However, the FET drain-source capacitance and gate charge cannot be ignored. The zero voltage switch (ZVS) transition timing is dependent on the transformer's leakage inductance and the capacitance at the node between the upper FET source and the lower FET drain. The node capacitance is comprised of the drain-source capacitance of the FETs and the transformer parasitic capacitance. The leakage inductance and capacitance form an LC resonant tank circuit which determines the duration of the transition. The amount of energy stored in the LC tank circuit determines the transition voltage amplitude. If the leakage inductance energy is too low, ZVS operation is not possible and near or partial ZVS operation occurs. As the leakage energy increases, the voltage amplitude increases until it is clamped by the FET body diode to ground or VIN, depending on which FET conducts. When the leakage energy exceeds the minimum required for ZVS operation, the voltage is clamped until the energy is transferred. This behavior increases the time window for ZVS operation.This behavior is not without consequences, however. The transition time and the period of time during which the voltage is clamped reduces the effective duty cycle. The gate charge affects the switching speed of the FETs. Higher gate charge translates into higher drive requirements and/or slower switching speeds. The energy required to drive the gates is dissipated as heat. The maximum input voltage, VIN, plus transient voltage, determines the voltage rating required. With a maximum input voltage of 53V for this application, and if we allow a 10% adder for transients, a voltage rating of 60V or higher will suffice.
FIGURE 4D. INT. LAYER 3: 2 TURNS PRIMARY WINDING
FIGURE 4E. INT. LAYER 4: 1 TURN SECONDARY WINDING
FIGURE 4F. BOTTOM LAYER: 1 TURN SECONDARY AND SR WINDINGS
11
ISL6744
The RMS current through each primary side FET can be determined from EQ. 8, substituting 5A of primary current for IOUT (assuming 100% duty cycle). The result is 3.5A RMS. Fairchild FDS3672 FETs, rated at 100V and 7.5A (Rdson = 22m), were selected for the half-bridge switches. The synchronous rectifier FETs must withstand approximately one half of the input voltage assuming no switching transients are present. This suggests a device capable of withstanding at least 30V is required. Empirical testing in the circuit revealed switching transients of 20V were present across the device indicating a rating of at least 60V is required. The RMS current rating of 7.07A for each SR FET requires a low Rdson to minimize conduction losses, which is difficult to find in a 60V device. It was decided to use two devices in parallel to simplify the thermal design. Two Fairchild FDS5670 devices are used in parallel for a total of four SR FETs. The FDS5670 is rated at 60V and 10A (Rdson = 14m). Once the estimated transition time is determined, it must be verified directly in the application. The transformer leakage inductance was measured at 125nH and the combined capacitance was estimated at 2000pF. Calculations indicate a transition period of ~ 25ns. Verification of the performance yielded a value of TD closer to 45ns. The remainder of the switching half-period is the charge time, TC, and can be found from
-9 1 1 T C = --------------- - T D = --------------------------------- - 45 * 10 = 2.08 3 2 * FS 2 * 235 * 10
s (EQ. 12)
where FS is the converter switching frequency. Using Fig. 3, the capacitor value appropriate to the desired oscillator operating frequency of 470kHz can be selected. A CT value of 100pF, 150pF, or 220pF is appropriate for this frequency. A value of 150pF was selected. To obtain the proper value for RTD, EQ. 3 is used. Since there is a 10ns propagation delay in the oscillator circuit, it must be included in the calculation. The value of RTD selected is 10k.
Oscillator Component Selection
The desired operating frequency of 235kHz for the converter was established in the Design Criteria section. The oscillator frequency operates at twice the frequency of the converter because two clock cycles are required for a complete converter period. During each oscillator cycle the timing capacitor, CT, must be charged and discharged. Determining the required discharge time to achieve zero voltage switching (ZVS) is the critical design goal in selecting the timing components. The discharge time sets the deadtime between the two outputs, and is the same as ZVS transition time. Once the discharge time is determined, the remainder of the period becomes the charge time. The ZVS transition duration is determined by the transformer's primary leakage inductance, Llk, by the FET Coss, by the transformer's parasitic winding capacitance, and by any other parasitic elements on the node. The parameters may be determined by measurement, calculation, estimate, or by some combination of these methods.
L lk * ( 2C oss + C xfrmr ) t zvs ------------------------------------------------------------------2 s (EQ. 10)
Output Filter Design
The output filter inductor and capacitor selection is simple and straightforward. Under steady state operating conditions the voltage across the inductor is very small due to the large duty cycle. Voltage is applied across the inductor only during the switch transition time, about 45ns in this application. Ignoring the voltage drop across the SR FETs, the voltage across the inductor during the on time with VIN = 48V is
V IN * N S * ( 1 - D ) V L = V S - V OUT = ----------------------------------------------- 250 2N P mV (EQ. 13)
where VL is the inductor voltage VS is the voltage across the secondary winding VOUT is the output voltage If we allow a current ramp, I, of 5% of the rated output current, the minimum inductance required is
V L * T ON 0.25 * 2.08 L ------------------------ = ---------------------------- = 1.04 I 0.5 H (EQ. 14)
Device output capacitance, Coss, is non-linear with applied voltage. To find the equivalent discrete capacitance, Cfet, a charge model is used. Using a known current source, the time required to charge the MOSFET drain to the desired operating voltage is determined and the equivalent capacitance is calculated.
Ichg * t Cfet = ------------------V F (EQ. 11)
An inductor value of 1.5H, rated for 18A was selected. With a maximum input voltage of 53V, the maximum output voltage is about 13V. The closest higher voltage rated capacitor is 16V. Under steady state operating conditions the ripple current in the capacitor is small, so it would seem appropriate to have a low ripple current rated capacitor. However, a high rated ripple current capacitor was selected based on the nature of the intended load, multiple buck
12
ISL6744
regulators. To minimize the output impedance of the filter, a SANYO OSCON 16SH150M capacitor in parallel with a 22F ceramic capacitor were selected. implication is that the converter can not supply the same output current in current limit that it can supply under steady state conditions. The peak current limit setpoint must take this behavior into consideration. A 3.32 current sense resistor was selected for the rectified secondary of current transformer T2, corresponding to a peak current limit setpoint of 16.5A.
Current Limit Threshold
The current limit threshold is fixed at 0.6V nominal, which is the reference to the overcurrent protection comparator. The current level that corresponds to the overcurrent threshold must be chosen to allow for the dynamic behavior of an open loop converter. In particular, the low inductor ripple current under steady state operation increases significantly as the duty cycle decreases.
Performance
The major performance criteria for the converter are efficiency, and to a lesser extent, load regulation. Efficiency, load regulation and line regulation performance are demonstrated in the following Figures. As expected, the output voltage varies considerably with line and load when compared to an equivalent converter with a closed loop feedback. However, for applications where tight regulation is not required, such as those applications that use downstream DC-DC converters, this design approach is viable.
100 95
14 13 12 11 10 9 8 0.9950 V (L1:1) I (L1) 0.9960 0.9970 0.9980 0.9990 1.000 TIME (ms)
EFFICIENCY (%)
90 85 85 75
FIGURE 5. STEADY STATE SECONDARY WINDING VOLTAGE AND INDUCTOR CURRENT
15
70
0
1
2
3
4
5
6
7
8
9
10
LOAD CURRENT (A)
FIGURE 7. EFFICIENCY vs LOAD VIN = 48V
10 12.5 12.25 OUTPUT VOLTAGE (V) 5 0.986 0.988 0.990 0.992 0.994 0.996 0.998 1.000 12 11.75 11.5 11.25 11
TIME (ms) V (L1:1) I (L1)
FIGURE 6. SECONDARY WINDING VOLTAGE AND INDUCTOR CURRENT DURING CURRENT LIMIT OPERATION
Figures 5 and 6 show the behavior of the inductor ripple under steady state and overcurrent conditions. In this example, the peak current limit is set at 11A. The peak current limit causes the duty cycle to decrease resulting in a reduction of the average current through the inductor. The 13
0
1
2
3
4
5
6
7
8
9
10
LOAD CURRENT (A)
FIGURE 8. LOAD REGULATION AT VIN = 48V
ISL6744
13.5 13 OUTPUT VOLTAGE (V) 12.5 12 11.5 11 10.5 42
43
44
45
46
47
48
49
50
51
52
53
INPUT VOLTAGE (V)
FIGURE 9. LINE REGULATION AT IOUT = 1A
Waveforms
Typical waveforms can be found in the following Figures. Figure 10 shows the output voltage ripple and noise at a 5A.
FIGURE 11. FET DRAIN-SOURCE VOLTAGE
FIGURE 12. FET D-S VOLTAGE NEAR-ZVS TRANSITION FIGURE 10. OUTPUT RIPPLE AND NOISE - 20MHz BW
Figures 11 and 12 show the voltage waveforms at the switching node shared by the upper FET source and the lower FET drain. In particular, Figure 12 shows near ZVS operation at 5A of load when the upper FET is turning off and the lower FET is turning on. ZVS operation occurs completely, implying that all the energy stored in the node capacitance has been recovered. Figure 13 shows the switching transition between outputs, OUTA and OUTB during steady state operation. The deadtime duration of 46.9ns is clearly shown. A 2.7V zener is added between the Vdd pins of ISL6700 and ISL6744, in order to ensure that the PWM turns on after the driver has turned on. Figure 14 shows the soft-start function.
FIGURE 13. OUTA - OUTB TRANSITION
14
ISL6744
FIGURE 14. OUTPUT SOFT-START
Component List
REFERENCE DESIGNATOR C1 C2, C3 C4 C5 C6, C15 C7 C8 C9 C10, C11, C12, C13, C14 C16 C18 CR1, CR2 CR3 CR4 D1 D2 L1 L2 L3 P1, P2, P3, P4 Q5 QL, QH NPN Replace Replace 190nH 1.5H Short VALUE 1.0F 3.3F 1.0F 0.1F 4.7F Open 22F 150F 1000pF 150pF 0.01F Capacitor, 1812, X7R, 100V, 20% Capacitor, 1812, X5R, 50V, 20% Capacitor, 0805, X5R, 16V, 10% Capacitor, 0603, X7R, 16V, 10% Capacitor, 0805, X5R, 10V, 20% Capacitor, 0603, Open or Optional Discrete Stray Capacitance Capacitor, 1812, X5R, 16V, 20% Capacitor, Radial, Sanyo 16SH150M Capacitor, 0603, X7R, 50V, 10% Capacitor, 0603, COG, 16V, 5% Capacitor, 0603, X7R, 16V, 10% Diode, Schottky, BAT54S, 30V Diode, Schottky, BAT54, 30V Diode, Schottky, SMA, 100V, 2.1A Zener, 10V,Zetex BZX84C10ZXCT-ND Zener, 2.7V,Zetex BZX84C10ZXCT-ND Pulse, P2004T Bitech, HM73-301R5 Jumper or Optional Discrete Leakage Inductance Keystone, 1514-2 Transistor, ON MJD31C FET, Fairchild FDS3672, 100V DESCRIPTION
15
ISL6744 Component List
REFERENCE DESIGNATOR QR1, QR2, QR3, QR4 R1 R2 R5 R6 R7 R8, R9 R10 R11 R12 T1 T2 TP1, TP2, TP4, TP5, TP6 SP1 U1 U2 3.3 3.01K 5.11 205 75.0K 20.0 18 100 10.0K Custom Custom 5002 (Continued)
VALUE FET, Fairchild FDS5670, 60V Resistor, 2512, 1% Resistor, 2512, 1% Resistor, 0603, 1% Resistor, 0603, 1% Resistor, 0805, 1% Resistor, 0805, 1% Resistor, 2512, 1% Resistor, 0603, 1% Resistor, 0603, 1% Midcom 31718 Midcom 31719R Keystone Tektronix Scope Jack, 131-4353-00 Intersil ISL6700IB, SOIC8 Intersil ISL6744AU, MSOP8
DESCRIPTION
16
ISL6744 Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 E
INCHES SYMBOL MIN 0.037 0.002 0.030 0.010 0.004 0.116 0.116 MAX 0.043 0.006 0.037 0.014 0.008 0.120 0.120
MILLIMETERS MIN 0.94 0.05 0.75 0.25 0.09 2.95 2.95 MAX 1.10 0.15 0.95 0.36 0.20 3.05 3.05 NOTES 9 3 4 6 7 15o 6o Rev. 2 01/03
INDEX AREA
-B12 TOP VIEW 0.25 (0.010) GAUGE PLANE SEATING PLANE -C4X R1 R 0.20 (0.008) ABC
A A1 A2 b c D E1
4X L L1
e E L
0.026 BSC 0.187 0.016 0.199 0.028
0.65 BSC 4.75 0.40 5.05 0.70
A
A2
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
L1 N R
0.037 REF 8 0.003 0.003 5o 0o 15o 6o
0.95 REF 8 0.07 0.07 5o 0o
C a C L E1
C
R1 0
SIDE VIEW
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
17
ISL6744 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E

A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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